1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having a pocket ion region designed to suppress the short channel effect.
2. Description of the Related Art
Recently in the field of semiconductor devices, an SOI (silicon on insulator) structure, where a silicon (Si) layer is formed on an insulating layer, is being commercialized. Substrates having an SOI structure are, for example, an SOS (Silicon On Sapphire) substrate formed by growing a silicon thin film on a sapphire substrate by vapor phase epitaxial growth, an SIMOX (Separation by Ion implanted Oxygen) substrate formed by forming a silicon dioxide (SiO2) layer inside the silicon substrate by implanting oxygen ions into the silicon substrate and then performing heat treatment, or a substrate formed by bonding silicon substrates via an oxide film (wafer bonding). A semiconductor device having an SOI structure has various good characteristics compared with a conventional semiconductor device using bulk silicon. If an SOI structure is applied to a MOSFET, the insulating layer having the SOI structure is placed immediately below the element active area of the MOSFET. Thus, the parasitic capacitance to be added to the MOSFET can be dramatically decreased. Accordingly, the switching characteristic of the MOSFET can be improved, operation speed can be increased, power can be saved and reliability can be improved.
Lately as semiconductor devices are further miniaturized and the degree of integration further increases, the short channel effect has started to be taken seriously in the field of MOSFET. Short channel effect is a phenomena that the threshold voltage of a MOSFET drops when the channel length of the MOSFET (distance between the source and drain of the MOSFET) is short due to the miniaturization of the MOSFET. The major cause of the short channel effect is DIBL (Drain Induced Barrier Lowering), which decreases the barrier of the channel region against carriers when voltage is applied to the drain. The dropping of the threshold voltage increases as the channel length decreases. This is because the formation of the depletion layer into the channel region is promoted by an electric field that extends radially from the drain. In other words, the threshold voltage is apparently lower in an area near the source and drain than in the center portion of the channel region because of the electric field that exists radially. The influence of the area having an apparently lower threshold voltage on the threshold of an entire MOSFET is not major if the channel length is long. However, if the channel length is short because of miniaturization of the MOSFET, the ratio of the area, where the threshold voltage is apparently low to the entire channel area, becomes high. Therefore, the influence of this area on the threshold of an entire MOSFET increases accordingly.
One way of suppressing the short channel effect is forming a so called “pocket ion region” in the semiconductor layer, as disclosed in Japanese Patent Application Kokai (Laid-Open) No. 2003-46086, and T. Hori et al, “Deep Sub-micrometer Large-Angle-Tilt Implanted Drain (LATID) Technology,” IEEE Trans. Electron Dev., 39 (10), 2312 (1992). A pocket ion region is a region of which conductive type is the same as a channel region, and where impurities are diffused so as to contact the source-drain region near the gate electrode. The concentration of impurities is higher in the pocket ion region than in the channel region. By forming a pocket ion region, the growth of the depletion layer from the source-drain region can be suppressed, and the short channel effect can be suppressed.
The effect of suppressing the short channel effect is greater as the impurities concentration in the pocket ion region becomes higher. Therefore as MOSFET miniaturization progresses and short channel effect increases, pocket concentration tends to increase. Also the effect of suppressing the short channel effect is greater as the pocket position becomes deeper under the gate (i.e., becomes closer to the center of the lower face of the gate). Therefore, the pocket region tends to be formed by tilted ion implantation with a larger angle.
If the dosage (impurities concentration) in the pocket region increases, the impurities concentration in the channel region increases. Then the maximum depletion layer width decreases, and forming a complete depletion type transistor becomes difficult. A possible solution for avoiding such difficulty is forming a shallow (thin) pocket region from the Si layer surface to promote depletion of the area under the SOI layer. However, to achieve a sufficient depletion promotion, the impurities concentration peak depth of the ion implantation when a pocket is formed must be set to about 10 nm, which radically deteriorates the short channel effect suppression. Therefore, in order to form a pocket to be shallow (thin) from the Si surface layer without diminishing the short channel effect suppression, the pocket must be formed by tilted ion implantation with a large angle. Specifically, the depth of the pocket under the gate must be about the same as the overlap length of the LDD (Light Doped Drain) region, which is about 20 nm. Therefore about a 65° implantation angle is required. However, the angle of tilted ion implantation is restricted to be in a range where the shielding by the adjacent gate has no effect on the transistor characteristics, and therefore is limited to about 30° to 40°.